The present invention relates to methods for forming a wiring pattern of a printed-wiring board and, more particularly, relates to a method for forming a wiring pattern of a printed-wiring board, suitable for accurately forming a fine pattern at a high density.
A method has conventionally been practiced for forming a wiring pattern of a printed-wiring board, in which an etching resist corresponding to a wiring pattern is provided on the surface of a copper-clad laminate which is obtained by providing a copper foil on a insulating substrate, to etch away those portions except the wiring pattern. In the above etching method, however, a cross section of the wiring pattern results in a trapezoidal shape where width of the bottom portion toward the substrate is relatively wider, since the copper film under the resist is subjected also to side etching. For this reason, it has been difficult to obtain a sufficient wiring cross sectional area as the width of the wiring becomes closer to the thickness of the wiring due to an increased density of the wiring. Further, there has been a problem that it is difficult to form a fine wiring with a high accuracy, since processing variance in etching is large.
For this reason, a pattern-plating method is used to accurately form such high density wiring. The pattern plating method is the method for forming a wiring pattern on an insulating substrate in which: a plating resist of which the open area comprises the wiring pattern is provided on the surface of a copper-clad laminate; the resist open area is plated with copper; the copper plating pattern surface is furthermore plated with solder; and, after peeling off said plating resist, the copper foil at the foundation is etched away by using the solder plating as the etching resist.
In the above pattern plating method, however, the copper plating pattern is subjected to side etch in a similar manner as the above etching method when etching the foundation copper foil, resulting in a problem of reduced wiring pattern width and reduced cross sectional area. Thus, various methods have been proposed of forming a solder plating film also on the side wall portion of the copper plating pattern to prevent side etching of the wiring pattern when etching the foundation copper foil. The known methods, for example, includes: a method, as disclosed in Japanese Patent Laid-Open Nos.62-262489 and 63-69290, in which photoresist development is repeated to form a crevice between the plating resist and the copper plating pattern and solder plating is then applied thereto; and a method, as disclosed in Japanese Patent Laid-Open No.3-222392, in which a boundary crevice between the copper plating pattern and the plating resist which occurs due to the difference in thermal expansion between the copper-clad laminate and the photoresist is used, so as to directly form a solder film on the side wall portion of the copper plating pattern by repeating in an alternating manner plating currents of a suitable level and a lower level.
Both of the above prior art respectively have the problems as follows.
In the method of repeating photoresist development, since exposure development is performed twice, deviation in dimensions tends to occur, its application in forming a high density, high precision wiring pattern is difficult, and an increase in number of steps is also unavoidable.
On the other hand, the method of directly forming a solder film on the copper plating pattern side wall by alternately repeating plating currents of a suitable level and a lower level by using the crevice at the boundary between the copper plating pattern and the plating resist is regarded as an excellent method in that number of steps is not increased and deviation in dimensions is smaller. This method is characterized in that, in order to balance consumption due to deposition with supply by means of diffusion of solder metal ion at the boundary crevice between the resist and the copper plating pattern at the time of solder plating, the steps are repeated of: applying a suitable current of a relatively low current density for a predetermined time period to deposit solder corresponding to the metal ion amount within the crevice on the copper plating pattern side wall portion; and then supplying the metal ion by means of diffusion into the crevice while applying a low level current that is 10% or less of the suitable current for a predetermined time period. In this method, however, since the current is continually applied, there is a problem that the solder metal ion causes a deposition on the copper plating pattern side wall in the vicinity of the crevice entrance, prior to its diffusion into the bottom portion of the crevice--not enough provision is made to uniformly cover the entire portion of the side wall with solder. As a result, side etching amount becomes larger at the portion of the copper plating pattern side wall toward the substrate, since it is not sufficiently covered with the solder film, resulting in a problem that wiring resistance is increased due to reduced cross sectional area of the pattern.